The need to sift through massive datasets from applications in cybersecurity, social media, financial transactions, and sensor feeds, is driving the design of novel architectures. There are few programming models and generalized processor architectures that can support the irregular memory accesses and fine grained concurrency requirements of graph analytics well while also providing accelerated run-time support. In this talk, Bader presents the hardware-software co-design of a graph analytics chip, such as in the DARPA HIVE program. In HIVE, Bader leads the Software Toolkit for Accelerating GrapH AlgoRithms on HIVE Processors (SHARP) project (joint with Georgia Tech and USC) to design a graph processing framework with Intel and Qualcomm. Unlike traditional high performance computing applications, solving analytics problems at scale often raises new challenges because of the sparsity and lack of locality in the data, the need for research on scalable algorithms and architectures, and development of frameworks for solving these real-world problems on high performance computers. SHARP will overcome two key challenges of the HIVE program: 1) platform independent, supporting high levels of algorithm acceleration for diverse set of HIVE processor designs which are expected to include technologies such as near-memory computing, systems-in-package, scratchpad and flash memories, accelerated processing, and vector processing and 2) scalability for variety of problem areas for extremely large static and dynamic graphs with millions of vertices and edges. SHARP will exploit the data structures, memory layout, and graph primitive implementations synergistically with a novel data flow representation and optimizations to deliver 1000x performance improvement.
David A. Bader is Professor and Chair of the School of Computational Science and Engineering at Georgia Institute of Technology. He is a Fellow of the IEEE and AAAS and advises the White House, most recently on the National Strategic Computing Initiative (NSCI). Dr. Bader is a leading expert in solving global grand challenges in science, engineering, computing, and data science. His interests are at the intersection of high-performance computing and real-world applications, including cybersecurity, massive-scale analytics, and computational genomics, and he has co-authored over 230 articles in peer-reviewed journals and conferences. Dr. Bader served as Editor-in-Chief of the IEEE Transactions on Parallel and Distributed Systems and is on the editorial board of several leading journals. Dr. Bader has served as a lead scientist in several DARPA programs including High Productivity Computing Systems (HPCS) with IBM, Ubiquitous High Performance Computing (UHPC) with NVIDIA, Anomaly Detection at Multiple Scales (ADAMS), Power Efficiency Revolution For Embedded Computing Technologies (PERFECT), Hierarchical Identify Verify Exploit (HIVE), and Software-Defined Hardware (SDH). He has also served as Director of the Sony-Toshiba-IBM Center of Competence for the Cell Broadband Engine Processor. Bader is a cofounder of the Graph500 List for benchmarking “Big Data” computing platforms. Bader is recognized as a “RockStar” of High Performance Computing by InsideHPC and as HPCwire’s People to Watch in 2012 and 2014.