Enhancing Cache Coherent Architectures with access patterns for embedded manycore systems


One of the key challenges in advanced micro-architecture is to provide high performance hardware-components that work as application accelerators. In this paper, we present a Cache Coherent Architecture that optimizes memory accesses to patterns using both a hardware component and specialized instructions. The high performance hardware-component in our context is aimed at CMP (Chip Multi-Processing) and MPSoC (Multiprocessor System-on-Chip). A large number of applications targeted at embedded systems are known to read and write data in memory following regular memory access patterns. In our approach, memory access patterns are fed to a specific hardware accelerator that can be used to optimize cache consistency mechanisms by prefetching data and reducing the number of transactions. In this paper, we propose to analyze this component and its associated protocol that enhance a cache coherent system to perform speculative requests when access patterns are detected. The main contributions are the description of the system architecture providing the high-level overview of a specialized hardware component and the associated transaction message model. We also provide a first evaluation of our proposal, using code instrumentation of a parallel application.

2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012